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ir3504 page 1 july 28, 2009 data sheet xphase3 tm amd svid control ic description the ir3504 control ic combined with an xphase3 tm phase ic provides a full featured and flexible way to implement a complete amd svid power solution. it pr ovides outputs for both the vdd core and vddnb auxiliary planes required by the cpu. the ir3504 pr ovides overall system control and interfaces with a ny number of phase ics each driving and monitoring a s ingle phase. the xphase3 tm architecture results in a power supply that is smaller, less expensive, and e asier to design while providing higher efficiency t han conventional approaches. features 2 converter outputs for the amd processor vdd core and vddnb auxiliary planes amd serial vid interface independently programs bo th output voltages and operation both converter outputs boot to 2-bit ?boot? vid co des which are read and stored from the svc & svd parallel inputs upon the assertion of the enable in put pwrok input signal activates svid after successful boot start-up both converter outputs can be independently turned on and off through svid commands deassertion of pwrok prior to enable causes the co nverter output to transition to the stored pre- pwrok vid codes connecting the pwrok input to vccl disables svid a nd implements vfix mode with both output voltages programmed via svc & svd parallel inputs p er the 2 bit vfix vid codes pg monitors output voltage, pg will deassert if ei ther ouput voltage out of spec 0.5% overall system set point accuracy programmable dynamic vid slew rates programmable vid offset (vdd output only) programmable output impedance (vdd output only) high speed error amplifiers with wide bandwidth of 20mhz and fast slew rate of 10v/us remote sense amplifiers provide differential sensi ng and require less than 50ua bias current programmable per phase switching frequency of 250k hz to 1.5mhz daisy-chain digital phase timing provides accurate phase interleaving without external components hiccup over current protection with delay during n ormal operation central over voltage detection and communication t o phase ics through iin (ishare) pin ovp disabled during dynamic vid down to prevent fa lse triggering detection and protection of open remote sense line s gate drive and ic bias linear regulator control wi th programmable output voltage and uvlo simplified power good (pg) output provides indicat ion of proper operation and avoids false triggering small thermally enhanced 32l mlpq (5mm x 5mm) pack age over voltage signal to system with over voltage de tection during powerup and normal operation ordering information device package order quantity ir3504mtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per reel * IR3504MPBF 32 lead mlpq (5 x 5 mm body) 100 piece strips * samples only downloaded from: http:///
ir3504 page 2 july 28, 2009 application circuit css/del1 cvdac1 css/del2 rvcclfb2 rosc rthermistor1 rvccldrv rfb13 phsout 26 pwrok 2 enable 3 svc 32 iin2 4 ocset2 7 vosns1+ 14 vdrp1 22 pg 31 iin1 21 clkout 25 vcclfb 29 vccl 28 phsin 27 vosns2- 12 eaout1 17 vout1 15 vdac1 19 vdac2 6 fb2 9 rosc 23 lgnd 24 svd 1 fb1 16 vccldrv 30 ss/del1 20 vout2 10 ocset1 18 vonsn1- 13 vosns2+ 11 ss/del2 5 eaout2 8 ir3504 control ic q1 vddnb sense + rocset1 vddnb sense - rvcclfb1 rvdac1 cvccl power good to vddnb remote sense phsin 12v svc svd vdd sense - vdd sense + phsout rocset2 clkout vdac1 ishare1 eaout1 ccp21 ccp22 rcp2 enable 12v cfb2 rfb21 rfb22 3 wire analog control bus to vddnb phase ics vccl to converters to vdd remote sense 2 wire digital daisy chain bus to vdd & vddnb phase ics to phase ic vccl & gate drive bias phase clock input to last phase ic of vdd ishare2 pwrok rvdac2 vdac2 cvdac2 rcp1 ccp11 rfb11 cdrp1 rdrp1 cfb1 ccp12 rfb12 eaout2 3 wire analog control bus to vdd phase ics load line ntc thermistor; locate close to vdd power stage figure 1 ? ir3504 application circuit pin description pin# pin symbol pin description 1 svd svd (serial vid data) is a bidirectional sign al that is an input and open drain output for both master (amd processor) and slave (ir3504), requires an external bias voltage and should not be floated 2 pwrok system wide power good signal and input to the ir3504. when asserted, the ir3504 output voltage is programmed through the svi d interface protocol. connecting this pin to vccl enables vfix mode. 3 enable enable input. a logic low applied to this pin puts the ic into fault mode. a logic high on the pin enables the converter and causes the svc and svd input states to be decoded and stored, determining the 2-bit boot vid. do not float this pin as the logic state will be undefined. 4 iin2 output 2 average current input from the outp ut 2 phase ic(s). this pin is also used to communicate over voltage condition to the output 2 phase ics. 5 ss/del2 programs output 2 startup and over curren t protection delay timing. connect an external capacitor to lgnd to program. 6 vdac2 output 2 reference voltage programmed by th e svid inputs and error amplifier non- inverting input. connect an external rc network to lgnd to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 7 ocset2 programs the output 2 constant converter o utput current limit and hiccup over- current threshold through an external resistor tied to vdac2 and an internal current source from this pin. over-current protection can b e disabled by connecting a resistor from this pin to vdac2 to program the thre shold higher than the possible signal into the iin2 pin from the phase ics but no greater than 5v (do not float this pin as improper operation will occur). downloaded from: http:///
ir3504 page 3 july 28, 2009 pin# pin symbol pin description 8 eaout2 output of the output 2 error amplifier. 9 fb2 inverting input to the output 2 error amplifi er. 10 vout2 output 2 remote sense amplifier output. 11 vosen2+ output 2 remote sense amplifier input. c onnect to output at the load. 12 vosen2- output 2 remote sense amplifier input. c onnect to ground at the load. 13 vosen1- output 1 remote sense amplifier input. c onnect to ground at the load. 14 vosen1+ output 1 remote sense amplifier input. c onnect to output at the load. 15 vout1 output 1 remote sense amplifier output. 16 fb1 inverting input to the output 1 error amplif ier. converter output voltage can be increased from the vdac1 voltage with an external r esistor connected between vout1 and this pin (there is an internal current si nk at this pin). 17 eaout1 output of the output 1 error amplifier. 18 ocset1 programs the output 1 constant converter output current limit and hiccup over- current threshold through an external resistor tied to vdac1 and an internal current source from this pin. over-current protection can b e disabled by connecting a resistor from this pin to vdac1 to program the thre shold higher than the possible signal into the iin1 pin from the phase ics but no greater than 5v (do not float this pin as improper operation will occur). 19 vdac1 output 1 reference voltage programmed by t he svid inputs and error amplifier non- inverting input. connect an external rc network to lgnd to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 20 ss/del1 programs output 1 startup and over curre nt protection delay timing. connect an external capacitor to lgnd to program. 21 iin1 output 1 average current input from the out put 1 phase ic(s). this pin is also used to communicate over voltage condition to phase ics. 22 vdrp1 output 1 buffered iin1 signal. connect an external rc network to fb1 to program converter output impedance. 23 rosc/ovp connect a resistor to lgnd to program o scillator frequency and ocset1, ocset2, fb1, fb2, vdac1, and vdac2 bias currents. oscillato r frequency equals switching frequency per phase. the pin voltage is 0.6v during normal operation and higher than 1.6v if over-voltage condition is detected. 24 lgnd local ground for internal circuitry and ic substrate connection. 25 clkout clock output at switching frequency multi plied by phase number. connect to clkin pins of phase ics. 26 phsout phase clock output at switching frequency per phase. connect to phsin pin of the first phase ic. 27 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 28 vccl output of the voltage regulator, and power input for clock oscillator circuitry. connect a decoupling capacitor to lgnd. 29 vcclfb non-inverting input of the voltage regula tor error amplifier. output voltage of the regulator is programmed by the resistor divider con nected to vccl. 30 vccldrv output of the vccl regulator error ampli fier to control external transistor. the pin senses 12v power supply through a resistor. 31 pg power good signal implemented with an open co llector output that drives low during startup and under any external fault condition. als o, if any of the voltage planes fall out of spec, it will drive low. connect external pu ll-up. (output voltage out of spec is defined as 350mv to 240mv below vdac voltages) 32 svc svc (serial vid clock) is an open drain outp ut of the processor and input to ir3504, requires an external bias voltage and shoul d not be floated downloaded from: http:///
ir3504 page 4 july 28, 2009 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltages are absolute voltages referenced to th e lgnd pin. operating junction temperature?????..0 to 150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standar d msl rating???????????????2 reflow temperature???????????.260 o c pin # pin name v max v min i source i sink 1 svd 8v -0.3v 1ma 10ma 2 pwrok 8v -0.3v 1ma 1ma 3 enable 3.5v -0.3v 1ma 1ma 4 iin2 8v -0.3v 5ma 1ma 5 ss/del2 8v -0.3v 1ma 1ma 6 vdac2 3.5v -0.3v 1ma 1ma 7 ocset2 8v -0.3v 1ma 1ma 8 eaout2 8v -0.3v 25ma 10ma 9 fb2 8v -0.3v 1ma 1ma 10 vout2 8v -0.3v 5ma 25ma 11 vosen2+ 8v -0.5v 5ma 1ma 12 vosen2- 1.0v -0.5v 5ma 1ma 13 vosen1- 1.0v -0.5v 5ma 1ma 14 vosen1+ 8v -0.5v 5ma 1ma 15 vout1 8v -0.3v 5ma 25ma 16 fb1 8v -0.3v 1ma 1ma 17 eaout1 8v -0.3v 25ma 10ma 18 ocset1 8v -0.3v 1ma 1ma 19 vdac1 3.5v -0.3v 1ma 1ma 20 iin1 8v -0.3v 5ma 1ma 21 ss/del1 8v -0.3v 1ma 1ma 22 vdrp1 8v -0.3v 35ma 1ma 23 rosc/ovp 8v -0.3v 1ma 1ma 24 lgnd n/a n/a 20ma 1ma 25 clkout 8v -0.3v 100ma 100ma 26 phsout 8v -0.3v 10ma 10ma 27 phsin 8v -0.3v 1ma 1ma 28 vccl 8v -0.3v 1ma 20ma 29 vcclfb 3.5v -0.3v 1ma 1ma 30 vccldrv 10v -0.3v 1ma 50ma 31 pg vccl + 0.3v -0.3v 1ma 20ma 32 svc 8v -0.3v 1ma 1ma downloaded from: http:///
ir3504 page 5 july 28, 2009 recommended operating conditions for reliable opera tion with margin 4.75v vccl 7.5v, -0.3v vosen-x 0.3v, 0 o c t j 100 o c, 7.75 k r osc 50 k , c ss/delx = 0.1uf electrical characteristics the electrical characteristics involve the spread o f values guaranteed within the recommended operatin g conditions (unless otherwise specified). typical va lues represent the median values, which are related to 25c. parameter test condition min typ max unit svid interface threshold increasing (note 1) 0.850 0.950 1.05 v threshold decreasing (note 1) 550 650 750 mv svc & svd input thresholds threshold hysteresis (note 1) 195 300 405 mv bias current 0v v(x) 3.5v, svd not asserted -5 0 5 ua svd low voltage i(svd)= 3ma 20 300 mv svd output fall time 0.7 x vddio to 0.3vddio, 1.425v vddio 1.9v, 10 pf cb 400 pf, cb=capacitance of one bus line (note 1) 20+ 0.1 xcb(pf) 250 ns pulse width of spikes suppressed by the input filter note 1 97 260 410 ns oscillator phsout frequency -10% see figure 2 +10% khz rosc voltage 0.57 0.600 0.630 v clkout high voltage i(clkout)= -10 ma, measure v(vc cl) ? v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout high voltage i(phsout)= -1 ma, measure v(vcc l) ? v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % vdrp1 buffer amplifier input offset voltage v(vdrp1) ? v(iin1), 0.5v v(iin) 3.3v -8 0 8 mv source current 0.5v v(iin1) 3.3v 2 30 ma sink current 0.5v v(iin1) 3.3v 0.2 0.4 0.6 ma unity gain bandwidth note 1 8 mhz slew rate note 1 4.7 v/ s iin bias current -1 0 1 a remote sense differential amplifiers unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 0.5v v(vosenx+) - v(vosenx-) 1.6v, note 2 -3 0 3 mv source current 0.5v v(vosenx+) - v(vosenx-) 1.6v 0.5 1 1.7 ma sink current 0.5v v(vosenx+) - v(vosenx-) 1.6v 2 12 16 ma slew rate 0.5v v(vosenx+) - v(vosenx-) 1.6v 2 4 8 v/us vosen+ bias current 0.5 v < v(vosenx+) < 1.6v 30 5 0 ua vosen- bias current -0.3v vosenx- 0.3v, all vid codes 30 55 ua vosen+ input voltage range v(vccl)=7v 5.5 v low voltage v(vccl) =7v 250 mv high voltage v(vccl) ? v(voutx) 0.5 1 v soft start and delay start delay measure enable to eaoutx activation 1 2.9 3.5 ms start-up time measure enable activation to pg 3 8 13 ms downloaded from: http:///
ir3504 page 6 july 28, 2009 parameter test condition min typ max unit oc delay time v(iinx) ? v(ocsetx) = 500 mv 300 650 1000 us ss/delx to fbx input offset voltage with fbx = 0v, adjust v(ss/delx) until eaoutx drives high 0.7 1.4 1.9 v charge current -30 -50 -70 a oc delay/vid off discharge currents note 1 47 a fault discharge current 2.5 4.5 6.5 a hiccup duty cycle i(fault) / i(charge) 8 10 12 ua/ ua charge voltage 3.5 3.9 4.2 v delay comparator threshold relative to charge volta ge, ss/delx rising note 1 80 mv delay comparator threshold relative to charge volta ge, ss/delx falling note 1 130 mv delay comparator hysteresis note 1 60 mv discharge comp. threshold 150 200 300 mv over-current comparators input offset voltage 1v v(ocsetx) 3.3v -30 0 30 mv ocset bias current -5% vrosc(v)*1000 /rosc(k ) +5% a 2048-4096 count threshold adjust rosc value to find threshold 11.4 k 1024-2048 count threshold adjust rosc value to find threshold 32.5 k error amplifiers vid > 1.0v -0.65 0.65 % 0.8v vid 1.0v -8 +8 mv system set-point accuracy (deviation from table 1, 2, and 3 per test circuit in figures 2a & 2b) 0.5v vid < 0.8v -9 +9 mv input offset voltage measure v(fbx) ? v(vdacx)). n ote 2 -1 0 1 mv fb1 bias current -5% vrosc(v)*1000 /rosc(k ) +5% a fb2 bias current -1 0 1 a dc gain note 1 100 110 135 db bandwidth note 1 20 30 40 mhz slew rate note 1 5.5 12 20 v/ s sink current 0.4 0.85 1 ma source current 6.0 8.5 13.0 ma maximum voltage measure v(vccl) ? v(eaoutx) 500 780 950 mv minimum voltage 120 250 mv open control loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open control loop detection delay measure phsout pulse numbers from v(eaoutx) = v(vccl) to pg = low. 8 pulses enable input blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns vdac references source currents includes i(ocsetx) -8% 3000*vrosc(v) / rosc(k ) +8% a sink currents includes i(ocsetx) -12% 1000*vrosc(v) / rosc(k ) +12% a pg output under voltage threshold - voutx decreasing reference to vdacx -365 -315 -265 mv under voltage threshold - voutx increasing reference to vdacx -325 -275 -225 mv under voltage threshold hysteresis 5 53 110 mv downloaded from: http:///
ir3504 page 7 july 28, 2009 note 1: guaranteed by design, but not tested in production note 2: vdacx outputs are trimmed to compensate for error & amp remote sense amp input offsets parameter test condition min typ max unit output voltage i(pg) = 4ma 150 300 mv leakage current v(pg) = 5.5v 0 10 a vccl activation threshold i(pg) = 4ma, v(pg) = 300m v 1.73 3.5 v over voltage protection (ovp) comparators threshold at power-up 1.60 1.73 1.83 v voutx threshold voltage compare to v(vdacx) 190 24 0 280 mv ovp release voltage during normal operation compare to v(vdacx) -13 3 20 mv threshold during dynamic vid down 1.79 1.84 1.89 v dynamic vid detect comparator threshold note 1 25 50 75 mv propagation delay to iin measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(iinx) transition to > 0.9 * v(vccl). 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage v(vccldrv)=1.8v. measure v(vccl)-v(rosc/ovp) 0 0.2 v propagation delay to ovp measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(rosc/ovp) transition to >1v. 150 300 ns iin pull-up resistance 5 15 open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(voutx) < [v(vosenx+) ? v(lgnd)] / 2 35 62.5 90 mv vosen+ open sense line comparator threshold compare to v(vccl) 87 89.5 92 % vosen- open sense line comparator threshold 0.35 0.385 0.42 v sense line detection source currents v(voutx) = 10 0mv 200 500 700 ua vccl regulator amplifier reference feedback voltage 1.15 1.2 1.25 v vcclfb bias current -1 0 1 ua vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 89.0 93.5 9 7.0 % uvlo stop threshold compare to v(vccl) 81.0 85.0 89 .0 % hysteresis compare to v(vccl) 7.0 8.25 9.5 % enable, pwrok inputs threshold increasing 1.38 1.65 1.94 v threshold decreasing 0.8 0.99 1.2 v threshold hysteresis 470 620 770 mv bias current 0v v(x) 3.5v, svc not asserted -5 0 5 ua pwrok vfix mode threshold 3.3v (vccl +3.3)(v) / 2 vccl v general vccl supply current 4 10 15 ma downloaded from: http:///
ir3504 page 8 july 28, 2009 phsout frequency vs rrosc chart phsout frequency vs. rrosc 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 5 10 15 20 25 30 35 40 45 50 55 rrosc (kohm) frequency (khz) figure 2 - phout frequency vs. rrosc chart downloaded from: http:///
ir3504 page 9 july 28, 2009 system set point test converter output voltage is determined by the syste m set point voltage which is the voltage that appea rs at the fbx pins when the converter is in regulation. the s et point voltage includes error terms for the vdac digital-to- analog converters, error amp input offsets, and rem ote sense input offsets. the voltage appearing at t he vdacx pins is not the system set point voltage. system set point vol tage test circuits for outputs 1 and 2 are shown in figures 3a and 3b. cvdac1 + - + - rrosc + - rvdac1 rocset1 + - eaout1 fb1 ocset1 vdac1 vosen1- vosen1+ vout1 lgnd rosc irosc irosc eaout vosns- vdac buffer amplifier ifb1 rosc buffer amplifier 1.2v "fast" vdac isink isource ir3504 system set point voltage iocset1 current source generator remote sense amplifier error amplifier irosc figure 3a - output 1 system set point test circuit cvdac2 + - + - rrosc + - rvdac2 rocset2 + - vdac2 ocset2 fb2 eaout2 lgnd vout2 vosen2+ vosen2- irosc rosc vosns- eaout vdac buffer amplifier "fast" vdac 1.2v rosc buffer amplifier system set point voltage ir3504 isource isink irosc error amplifier remote sense amplifier current source generator iocset2 figure 3b - output 2 system set point test circuit downloaded from: http:///
ir3504 page 10 july 28, 2009 system theory of operation pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 4. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and feed-forward control is re alized. the pwm ramp slope will change with the input voltage a utomatically compensating for changes in the input voltage. the input voltage can change due to variations in t he silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. gnd vout1 vosns1+ dacin vcc vdac1 vout1 iin1 vdrp1 lgnd ishare phsin vosns1- csin- csin+ gatel eain gateh sw vin fb1 eaout1 clkout clkin phsout pgnd vccl vcch dacin vcc clkin phsout csin+ gatel eain gateh ishare phsin sw pgnd vccl vcch csin- phsin phsout vid6 vid6 irosc vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 gate drive voltage - + + + enable ramp discharge clamp body braking comparator ifb1 vdrp1 amp vdac clock generator current sense amplifier r s share adjust error amplifier reset dominant pwm latch error amplifier cout ir3504 control ic phase ic output 1 only pwm comparator pwm comparator - + + + ramp discharge clamp enable body braking comparator share adjust error amplifier reset dominant pwm latch current sense amplifier r s phase ic remote sense amplifier ccs rcs +- cfb1 rcs cbst + - ccs cbst + - + - ccp11 + - + - rfb12 rdrp1 cdrp1 rfb11 3k + - + - clk d q + - + - rcp1 + - 3k + - + - ccp12 clk d q + - figure 4 - pwm block diagram frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 250 kh z to 9 mhz by an external resistor. the control ic system cloc k signal (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock output (phsout) is connected to the phase clock input (phs in) of the first phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the last phase ic (phsout) is connected back to phsin of the control ic to complete the loop. during power up, t he control ic sends out clock signals from both clk out and phsout pins and detects the feedback at phsin pin t o determine the phase number and monitors for any f ault in the daisy chain loop. figure 5 shows the phase timi ng for a four phase converter. downloaded from: http:///
ir3504 page 11 july 28, 2009 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 5 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is set; the pwm ramp voltage begins to increase; the l ow side driver is turned off, and the high side dri ver is then turned on after the non-overlap time. when the pwm ramp voltage exceeds the error amplifier?s output v oltage, the pwm latch is reset. this turns off the high side dr iver and then turns on the low side driver after th e non-overlap time; it activates the ramp discharge clamp, which quickly discharges the internal pwm ramp capacitor to the output voltage of share adjust amplifier in phase ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease whi ch is appropriate given the low output to input vol tage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide ?single cycle transient response? where the inductor curren t changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the architecture is that differences in ground or input voltage at the phases have no effec t on operation since the pwm ramps are referenced t o vdac. figure 6 depicts pwm operating waveforms under vari ous conditions. downloaded from: http:///
ir3504 page 12 july 28, 2009 phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid fault) figure 6 pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this inc reases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as ?body braking? and is accompl ished through the ?body braking comparator? located in th e phase ic. if the error amplifier?s output voltage drops below the vdac voltage or a programmable voltage, this co mparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as shown in figure 7. the equation of the sensing netw ork is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. downloaded from: http:///
ir3504 page 13 july 28, 2009 figure 7 inductor current sensing and current sen se amplifier the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with the inductor, this is the only sense me thod that can support a single cycle transient resp onse. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 7. it s gain is nominally 34 at 25oc, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltag e loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the con trol ic and other phases through an on-chip 3k resistor connected to the ishare pin. the ishare p ins of all the phases are tied together and the voltage on the share bus repr esents the average current through all the inductor s and is used by the control ic for voltage positioning and curre nt limit protection. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compar ed with average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output c urrent; if current in a phase is larger than the av erage current, the share adjust amplifier of the phase will pull u p the starting point of the pwm ramp thereby decrea sing its duty cycle and output current. the current share amplifi er is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r cs c cs v o current sense amp csout i l v l v cs c downloaded from: http:///
ir3504 page 14 july 28, 2009 ir3504 theory of operation block diagram the block diagram of the ir3504 is shown in figure 8. the following discussions are applicable to eit her output plane unless otherwise specified. serial vid control the two serial vid interface (svid) pins svc and sv d are used to program the boot vid voltage upon ass ertion of enable while pwrok is de-asserted. see table 1 for the 2-bit boot vid codes. both vdac1 and vdac2 voltages will be programmed to the boot vid code un til pwrok is asserted. the boot vid code is stored by the ir3504 to be utilized again if pwrok is de-asserted . serial vid communication from the processor is enab led after the pwrok is asserted. addresses and dat a are serially transmitted in 8-bit words. the ir3504 ha s three fixed addresses to control vdac1, vdac2, or both vdac1 and vdac2 (see table 6 for addresses). the f irst data bit of the svid data word represents the psi_l bit and will be ignored by the ir3504 therefore this sy stem will never enter a power-saving mode. the rema ining data bits svid[6:0] select the desired vdacx regulation voltage as defined in table 3. svid[6:0] are the i nputs to the digital-to-analog converter (dac) which then provid es an analog reference voltage to the transconducta nce type buffer amplifier. this vdacx buffer provides a syst em reference on the vdacx pin. the vdacx voltage a long with error amplifier and remote sense differential ampli fier input offsets are post-package trimmed to prov ide a 0.5% system set-point accuracy, as measured in figures 3a and 3b. vdacx slew rates are programmable by properly selecting external series rc compensation networks located between the vdacx and the lgnd pins. the v dacx source and sink currents are derived off the extern al oscillator frequency setting resistor, r rosc . the programmable slew rate enables the ir3504 to smoothly transition the regulated output voltage throughout vid transi tions. this results in power supply input and output capacitor inrush currents along with output voltage overshoot to be well controlled. the two serial vid interface (svid) pins svc and sv d can also program the vfix vid voltage upon assert ion of enable while pwrok is equal to vccl. see table 2 f or the 2-bit vfix vid codes. both vdac1 and vdac2 voltages will be programmed to the vfix code. the svc and svd pins require external pull-up biasi ng and should not be floated. output 1 (vdd) adaptive voltage positioning the ir3504 provides adaptive voltage positioning (a vp) on the output1 plane only. avp helps reduces t he peak to peak output voltage excursions during load trans ients and reduces load power dissipation at heavy l oad. the circuitry related to the voltage positioning is sho wn in figure 9. resistor r fb1 is connected between the error amplifiers inverting input pin fb1 and the remote s ense differential amplifier output, vout1. an inter nal current sink on the fb1 pin along with r fb1 provides programmability of a fixed offset voltage above the vdac1 voltage. the offset voltage generated across r fb1 forces the converter?s output voltage higher to ma intain a balance at the error amplifiers inputs. the fb1 sink current is derived by the external resistor r rosc that programs the oscillator frequency. the vdrp1 pin voltage is a buffered reproduction of the iin1 pin which is connected to the current sha re bus ishare. the voltage on ishare represents the syste m average inductor current information. at each ph ase ic, an rc network across the inductor provides current information which is gained up 32.5x and then added to the vdac x voltage. this phase current information is provide d on the ishare bus via a 3k resistor in the phase ics. downloaded from: http:///
ir3504 page 15 july 28, 2009 dly out2 s r q q oc delay couter disable 0.86 svi (seriel vid interface) vout1 vid off dchg1 flt1 dchg1 vccl uvlo dis vout2 vccl disable vccl uvlo detection pulse1 ov1-2 ov2 ov1 + - metal to svid + - 25k + - + - back to pre-pwrok 2 bit vid ss/del2 phsout clkout enable pg vccldrv vcclfb rosc vccl phsin vosen1+ vout1 vdrp1 irosc dis eaout1 vdac1 lgnd vosen1- vid3 iin1 ocset1 fb1 vccl vccl flt2 vid7 phsin irosc vid3 irosc disable1 ivosen- vidsel uv1 phsout clkout fault disable irosc pwrok error amplifier delay comparator set dominant 3.9v ss/del cleared fault latch2 vout2 vid off 1v enable comparator vdac buffer amplifier d/a converter 1.65v disable vout2 vid on-the-fly high to low vccl regulator amplifier over voltage comparator 250ns blanking vccl uvl comparator 0.94 1.2v 0.6v rosc buffer amplifier current source generator power-up ok latch isink isource remote sense amplifier vdrp amplifier discharge comparator 80mv 120mv reset dominant dis ivosen1+ 200mv 1.6v 50mv 0.2v 0.4v vccl*0.9 ivosen1- 1.4v soft start clamp ifb 240mv ov fault latch set dominant oc limit comparator open daisy chain 4 open sense line detect comparators 60mv flt2 ichg 50ua open sense line1 oc2 after pg dis vdac2 iocset 8 pulse delay 1.08v vid0 vccl reset + - internal circuit bias + - 25k + - dchg2 open sense2 + - + - + - vccl uvlo 25k flt1 + - 25k + - open control loop comparator vccl vid3 + - + + - s r q open control1 detection pulse2 en en uv cleared fault latch1 set dominant + - 25k vid3 s r q + - open daisy dis + - idchg 4.5ua vosen2- vosen2+ eaout2 vdac2 iin2 ocset2 fb2 ov1 ss/del1 idchg1 47ua ovlatch + - vccl vccl 3.9v ss/del cleared fault latch1 vid7 reset dominant power-up ok latch delay comparator set dominant pg 0.2v discharge comparator 60mv 130mv vidsel ivosen- oc1 after pg disable2 open sense1 ichg 50ua irosc over voltage comparator vdac buffer amplifier error amplifier flt1 metal to svid svid to metal svid to svid detection pulse2 ov1 low to high reset reset ovlatch vid3 vout1 vid on-the-fly high to low high to low dis oc delay couter phsout dis dly out1 dly out2 dly out2 vout2 vid off vdac2 ov2 dis uv2 en en oc2 bf pg svid enabled irosc dis dis vid3 vccl - 1.2v vout1 uv comparator dly out1 vout1 vid off vid3 phsout connection to vccl detection pulse1 + - uv2 275mv 315mv vout2 uv comparator oc1 bf pg + - uv1 vdac1 sscl fs2 pg svid to svid ov1_2 1.6v 50mv isink isource remote sense amplifier vccl*0.9 ivosen2- ivosen2+ 200mv 1.4v soft start clamp 0.4v dynamic vid2 down detect comparator 240mv oc limit comparator 4 open sense line detect comparators 60mv iocset open sense line2 1.08v sscl fs1 flt2 vccl reset vdac1 + - + - vid3 s r q irosc ov2 47ua + - idchg2 sscl fs1 s r q q open control2 vccl uvlo + - 25k + - dis vccl + - dis + - 275mv 315mv + - + - + + - svid to metal 25k vid3 + - + - + - s r q uv cleared fault latch2 set dominant + - 25k vccl + - s r q read & store pre-pwrok 2 bit vid sscl fs2 svc dis 8 pulse delay phsout dynamic vid1 down detect comparator vid3 flt1 open control loop comparator flt2 irosc open daisy phsout dly out1 ovlatch dis idchg 4.5ua vfix mode svd dchg2 figure 8 block diagram downloaded from: http:///
ir3504 page 16 july 28, 2009 table 1 ? 2-bit boot vid codes table 2 ? vfix mode 2 bit vid codes svc svd output voltage(v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 table 3 - amd 7 bit svid codes svid [6:0] voltage (v) svid [6:0] voltage (v) svid [6:0] voltage (v) svid [6:0] voltage (v) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110 _0000 0.5000 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110 _0001 0.5000 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110 _0010 0.5000 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110 _0011 0.5000 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110 _0100 0.5000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110 _0101 0.5000 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110 _0110 0.5000 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110 _0110 0.5000 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110 _1000 0.5000 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110 _1001 0.5000 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110 _1010 0.5000 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110 _1011 0.5000 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110 _1100 0.5000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110 _1101 0.5000 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110 _1110 0.5000 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110 _1111 0.5000 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111 _0000 0.5000 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111 _0001 0.5000 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111 _0010 0.5000 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111 _0011 0.5000 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111 _0100 0.5000 001_0101 1.2875 011_0101 0.8875 101_0101 0.5000 111_0101 0.5000 001_0110 1.2750 011_0110 0.8750 101_0110 0.5000 111_0110 0.5000 001_0111 1.2625 011_0111 0.8625 101_0111 0.5000 111_0111 0.5000 001_1000 1.2500 011_1000 0.8500 101_1000 0.5000 111_1000 0.5000 001_1001 1.2375 011_1001 0.8375 101_1001 0.5000 111_1001 0.5000 001_1010 1.2250 011_1010 0.8250 101_1010 0.5000 111_1010 0.5000 001_1011 1.2125 011_1011 0.8125 101_1011 0.5000 111_1011 0.5000 001_1100 1.2000 011_1100 0.8000 101_1100 0.5000 111_1100 off 001_1101 1.1875 011_1101 0.7875 101_1101 0.5000 111_1101 off 001_1110 1.1750 011_1110 0.7750 101_1110 0.5000 111_1110 off 001_1111 1.1625 011_1111 0.7625 101_1111 0.5000 111_1111 off svc svd output voltage(v) 0 0 1.4 0 1 1.2 1 0 1.0 1 1 0.8 downloaded from: http:///
ir3504 page 17 july 28, 2009 vosen1- csin- csin+ iin1 csin- eaout1 ishare vdrp1 phase ic phase ic ishare vout1 + - rfb1 current sense amplifier + - 3k 3k rdrp1 + - ... ... + - vdac vdac remote sense amplifier vdac1 vdac1 fb1 ifb current sense amplifier error amplifier vdrp amplifier control ic vosen1+ csin+ + - figure 9 adaptive voltage positioning + - eaout1 + - iin1 vdac1 ifb vdac1 control ic error amplifier rdrp1 vdrp amplifier vdrp1 rt rfb12 rfb11 fb1 vosen1+ vout1 vosen1- + - remote sense amplifier figure 10 temperature compensation of output1 ind uctor dcr downloaded from: http:///
ir3504 page 18 july 28, 2009 output 1 (vdd) adaptive voltage positioning (contin ued) the voltage difference between vdrp1 and fb1 repres ents the gained up average current information. pl acing a resistor r drp1 between vdrp1 and fb1 converts the gained up curre nt information (in the form of a voltage) into a current forced onto the fb1 pin. this current, whi ch can be calculated using (vdrp1-vdac1) / r drp1 , will vary the offset voltage produced across r fb1 . since the error amplifier will force the loop to maintain fb1 to equal the vdac1 reference voltage, the output regulation volt age will be varied. when the load current increase s, the adaptive positioning voltage v(vdrp1) increases acc ordingly. (vdrp1-vdac1) / r drp1 increases the voltage drop across the feedback resistor r fb1 , and makes the output voltage lower proportional t o the load current. the positioning voltage can be programmed by the resist or r drp1 so that the droop impedance produces the desired converter output impedance. the offset and slope of the converter output impedance are referenced to v dac1 and are not affected by changes in the vdac1 voltage. output1 inductor dcr temperature compensation a negative temperature coefficient (ntc) thermistor can be used for output1 inductor dcr temperature compensation. the thermistor should be placed close to the output1 inductors and connected in parallel with the feedback resistor, as shown in figure 10. the resis tor in series with the thermistor is used to reduce the nonlinearity of the thermistor. remote voltage sensing vosen x + and vosen x - are used for remote sensing and connected directl y to the load. the remote sense differential amplifiers are high speed, have low in put offset and low input bias currents to ensure ac curate voltage sensing and fast transient response. start-up sequence the ir3504 has a programmable soft-start function t o limit the surge current during the converter star t-up. a capacitor connected between the ss/del x and lgnd pins controls soft start timing, over-cur rent protection delay and hiccup mode timing. constant current sources an d sinks control the charge and discharge rates of t he ss/del x . figure 11 depicts the svid start-up sequence. if th e enable input is asserted and there are no faults, the ss/del x pin will begin charging, the pre-pwrok 2 bit boot v id codes are read and stored, and both vdac pins tr ansition to the pre-pwrok boot vid code. the error amplifier ou tput eaout x is clamped low until ss/del x reaches 1.4v. the error amplifier will then regulate the converte r?s output voltage to match the v(ss/del x )-1.4v offset until the converter output reaches the 2-bit boot vid code. t he ss/del x voltage continues to increase until it rises above the threshold of delay comparator where the pg outp ut is allowed to go high. the svid interface is act ivated upon pwrok assertion and the vdac x along with the converter output voltage will chang e in response to any svid commands. vccl under voltage, over current, or a low signal o n the enable input immediately sets the fault latch , which causes the eaout pin to drive low, thereby turning off the phase ic drivers. the pg pin also drives lo w and ss/del x discharges to 0.2v. if the fault has cleared, the fault latch will be reset by the ss/del x discharge comparator allowing another soft start charge cycle to occur. other fault conditions, such as output over voltage , open vosns sense lines, or an open phase timing d aisy chain set a different group of fault latches that can onl y be reset by cycling vccl power. these faults dis charge ss/del x , pull down eaout x and drive pg low. svid off codes turn off the converter by dischargin g ss/del x and pulling down eaoutx but do not drive pg low. upon receipt of a non-off svid code the converter w ill re-soft start and transition to the voltage rep resented by the svid code as shown in figure 11. the converter can be disabled by pulling the ss/del x pins below 0.6v. downloaded from: http:///
ir3504 page 19 july 28, 2009 svid off transistion svid programmed voltage svid transition startup time (12v) start delay vcc enable 1.4v vout pg 3.92v ss/del 4.0v normal operation vdacx svid set voltage 2-bit boot vid voltage eaout svid off command svid off command pwrok 2-bit boot vid on-hold 2-bit boot vid on-hold 0.5v svid on transistion svid on command svid on command 1.4v vid on the fly procession 0.8v svc svd 2-bit boot vid read & store 2-bit boot vid read & store svid transition figure 11 svid start-up sequence transitions downloaded from: http:///
ir3504 page 20 july 28, 2009 serial vid interface protocol and vid-on-the-fly tr ansition the ir3504 supports the amd svi bus protocol and th e amd server and desktop svi wire protocol which is based on fast-mode i 2 c. svid commands from an amd processor are communi cated through svid bus pins svc and svd. the svc pin of the ir3504 does not have an op en drain output since amd svid protocol does not su pport slave clock stretching. the ir3504 transitions from a 2-bit boot vid mode t o svi mode upon assertion of pwrok. the smbus send byte protocol is used by the ir3504 vid-on-the-fly trans actions. the ir3504 will wait until it detects a s tart bit which is defined as an svd falling edge while svc is high. a 7bit address code plus one write bit (low) should then follow the start bit. this address code will be compared against an internal address table and the ir3504 wi ll reply with an acknowledge ack bit if the address is one of the th ree stored addresses otherwise the ack bit will not be sent out. the svd pin is pulled low by the ir3504 to generate the ack bit. table 4 has the list of addresses re cognized by the ir3504. the processor should then transmit the 8-bit data w ord immediately following the ack bit. data bit 7 is the psi_l bit which is followed by the 7bit amd code. the ir 3504 replies again with an ack bit once the data is received. if the received data is not a vid-off command, the ir3 504 immediately changes the dac analog outputs to t he new target. vdac1 and vdac2 then slew to the new vid v oltages. see figure 12 for a send byte example. table 4 - svi send byte address table svi address [6:0] + wr description 110xx100b set vid only on output 1 110xx010b set vid only on output 2 110xx110b set vid on both output 1 and output 2 note: ?x? in the above table 4 means the bit could be either ?1? or ?0?. figure 12 send byte example downloaded from: http:///
ir3504 page 21 july 28, 2009 over-current hiccup protection after soft start the over current limit threshold is set by a resist or connected between ocset x and vdac x pins. figure 13 shows the hiccup over-current protection with delay after pg is asserted. the delay is required since over-c urrent conditions can occur as part of normal operation du e to load transients or vid transitions. if the iin x pin voltage, which is proportional to the average current plus vdac x voltage, exceeds the ocsetx voltage after pg is asserted, it will initiate the discharge of the capacitor at ss/del x through the discharge current 47ua. if the over-current condition persists long e nough for the ss/del x capacitor to discharge below the 120mv offset of the delay comparator, the fault latch wil l be set which will then pull the error amplifier?s output low to stop phase ic switching and will also de-asserting the p g signal. the ss/del capacitor will then continue t o be discharged by a 4.5 ua current until it reaches 200 mv where the fault latch will reset to allow anoth er soft start cycle to occur. the output current is not controlle d during the delay time. if an over-current conditi on is again encountered during the soft start cycle, the over-c urrent action will repeat and the converter will be in hiccup mode. over-current protection (output shorted) normal operation 3.87v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.92v ss/del iout vout vrrdy 1.4v enable ocp threshold 4.0v normal start-up (output shorted) normal start-up internal oc delay figure 13 hiccup over-current waveforms linear regulator output (vccl) the ir3504 has a built-in linear regulator contro ller, and only an external npn transistor is needed to create a linear regulator. the output voltage of the linear regulator can be programmed between 4.75v and 7.5v by the resistor divider at vcclfb pin. the regulator outpu t powers the gate drivers and other circuits of the phase ics along with circuits in the control ic, and the volt age is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capa citor at the vccl pin. as with any linear regulator , due to stability reasons, there is an upper limit to the m aximum value of capacitor that can be used at this pin and it?s a function of the number of phases used in the multip hase architecture and their switching frequency. fi gure 14 shows the stability plots for the linear regulator with 5 phases switching at 750 khz. an external 5v can be connected to this pin to repl ace the linear regulator with appropriate selection of the vcclfb resistor divider, and vccldrv resistor. when using an external vccl, it?s essential to adjust it such that vcclfb is slightly less than the 1.19v reference voltage. this condition ensures that the vccldrv pin doesn?t load the rosc pin. the switching frequency, fb1 bias current , vdac slew rate and ocset point are derived from t he loading current of rosc pin. downloaded from: http:///
ir3504 page 22 july 28, 2009 figure 14 vccl regulator stability with 5 phases and phsout equals 750 khz vccl under voltage lockout (uvlo) the ir3504 does not directly monitor vcc for under voltage lockout but instead monitors the system vcc l supply voltage since this voltage is used for the gate dri ve. as vcc begins to rise during power up, the vccl drv pin will be high impedance therefore allowing vccl to roughl y follow vcc-npn vbe until vccl is above 94% of the voltage set by resistor divider at vcclfb pin. at this poin t, the ov x and uv cleared fault latches will be released. if vccl voltage drops below 86% of the set value, the ss/del cleared fault latch will be set. vid off codes svid off codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down ea out x voltage and discharging ss/del x through the 50ua discharge current, but do not dri ve pg low. upon receipt of a non-off svid code the converter will turn on and tr ansition to the voltage represented by the svid as shown in figure 10. voltage regulator ready (pg) the pg pin is an open-collector output and should h ave an external pull-up resistor. during soft start , pg remains low until the output voltage is in regulation and s s/del x is above 3.9v. the pg pin becomes low if enable is low, vccl is below 86% of target, an over current condit ion occurs for at least 1024 phsout clocks prior to pg, an over current condition occurs after pg and ss/del x discharges to the delay threshold, an open phase ti ming daisy chain condition occurs, vosns lines are detected op en, vout x is 315mv below vdac x , or if the error amp is sensed as operating open loop for 8 phsout cycles. a high level at the pg pin indicates that the conve rter is in operation with no fault and ensures the output volt age is within the regulation. pg monitors the output voltage. if any of the volta ge planes fall out of regulation, pg will become lo w, but the vr continues to regulate its output voltages. the pwro k input may or may not de-assert prior to the volta ge planes falling out of specification. output voltage out of spec is defined as 315mv to 275mv below nominal vo ltage. vid on-the-fly transition which is a voltage plane tran sitioning between one voltage associated with one v id code and a voltage associated with another vid code is not con sidered to be out of specification. a pwrok de-assert while enable is high results in a ll planes regulating to the previously stored 2-bit boot vid. if the 2-bit boot vid is higher than the vid prior to pwrok de-assertion, this transition will not be tre ated as vid on- the-fly and if either of the two outputs is out of spec high, pg will be pulled down. downloaded from: http:///
ir3504 page 23 july 28, 2009 open control loop detection the output voltage range of error amplifier is cont inuously monitored to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier outp ut above vccl-1.08v for 8 phsout switching cycles, the fault latch is set. the fault latch can only be cleared b y cycling the power to vccl. load current indicator output the vdrp pin voltage represents the average current of the converter plus the dac voltage. the load cu rrent information can be retrieved by using a differentia l amplifier to subtract vdac1 voltage from the vdrp 1 voltage. enable input pulling the enable pin below 0.8v sets the fault la tch. forcing enable to a voltage above 1.94v resul ts in the pre-pwrok 2 bit vid codes off the svd and svc pins to be read and stored. ss/del x pins are also allowed to begin their power-up cycles. over voltage protection (ovp) output over-voltage might occur due to a high side mosfet short or if the output voltage sense path is compromised. if the over-voltage protection compara tors sense that either vout x pin voltage exceeds vdac x by 240mv, the over voltage fault latch is set which pu lls the error amplifier output low to turn off the converter power stage. the ir3504 communicates an ovp condition to the system by raising the rosc/ovp pin voltage to w ithin v(vccl) ? 1.2 v. an ovp condition is also communic ated to the phase ics by forcing the iin pin (which is tied to the ishare bus and ishare pins of the phase ics) to vccl as shown in figure 15. in each phase ic, the ovp circuit overrides the normal pwm operation to ensur e the low side mosfet turn-on within approximately 150ns. the low side mosfet will remain on until the ishare pins fall below v(vccl) - 800mv. an over voltage fault condition is latched in the ir3504 and can only be cleared by cycling the power to vccl. during dynamic vid down at light to no load, false ovp triggering is prevented by increasing the ovp t hreshold to a fixed 1.6v whenever a dynamic vid is detected and t he difference between output voltage and the fast i nternal vdac is more than 50mv, as shown in figure 16. the over-voltage threshold is changed back to vdac+240m v if the difference between output voltage and the fast internal vdac is less than 50mv. the overall system must be considered when designin g for ovp. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase c onverter will be triggered thus providing effective protection without damage as long as all pcb traces and compon ents are sized to handle the worst-case maximum cur rent. if this is not possible, a fuse can be added in the in put supply to the multiphase converter. downloaded from: http:///
ir3504 page 24 july 28, 2009 after ovp fault latch output voltage (vout) ovp threshold iin (phase ic ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 15 - over-voltage protection during normal o peration output voltage (vo) vid down normal operation vdac vid ov threshold vdac + 240mv 1.84v normal operation vid up low vid vdac 50mv 50mv figure 16 over-voltage protection during dynamic vi d downloaded from: http:///
ir3504 page 25 july 28, 2009 open remote sense line protection if either remote sense line vosen x + or vosen x - is open, the output of remote sense amplifier (vo ut x ) drops. the ir3504 continuously monitors the vout x pin and if vout x is lower than 200 mv, two separate pulse currents are applied to the vosen x + and vosen x - pins to check if the sense lines are open. if vos en x + is open, a voltage higher than 90% of v(vccl) will be present at vosen x + pin and the output of open line detect comparator will be high. if vosen x - is open, a voltage higher than 400mv will be pres ent at vosen x - pin and the open line detect comparator output will be high. with either sense line open, the open sense line fault latch wi ll be set to force the error amplifier output low and immediatel y shut down the converter. ss/del x will be discharged and the open sense fault latch can only be reset by cycling the power to vccl. open daisy chain protection the ir3504 checks the daisy chain every time it pow ers up. it starts a daisy chain pulse on the phsout pin and detects the feedback at phsin pin. if no pulse come s back after 30 clkout pulses, the pulse is restart ed again. if the pulse fails to come back the second time, the o pen daisy chain fault is registered, and ss/del x is not allowed to charge. the fault latch can only be reset by cyc ling the power to vccl. after powering up, the ir3504 monitors phsin pin fo r a phase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse i s started on phsout pin. if the second started phsout pulse does not return on phsin, an open daisy chain fault is registered. phase number determination after a daisy chain pulse is started, the ir3504 ch ecks the timing of the input pulse at phsin pin to determine the phase number. downloaded from: http:///
ir3504 page 26 july 28, 2009 the fault table below describes ten different fault s that can occur during normal operation and how th e ir3504 ic will react to protect the supply and the load from possible damage. the fault types that can occur are listed in row one. row two and three describes type and the metho d of clearing the faults, respectively. the first f our faults are latched in the uv fault and require the vccl supply to be recycled (below uvlo threshold) to regain op eration. the rest of the faults, except for uvlo vout, are latch ed in a ss fault which do not need vccl supply recy cled, but instead will automatically resume operation when th ese fault conditions are no longer impinging on the system. most of the faults will disable the error amplifier (ea) and discharge the soft start capacitor. all o f the faults flag pgood. pgood returns to high impedance state (high) when the fault clears. the delay row shows reactio n time after detecting a fault condition. delays are provi ded to minimize the possibility of nuisance faults. additional flagged responses are used to communicate externally of a f ault event (over voltage) so additional action can be taken. system fault table fault type open daisy open sense open control over voltage disable vid_off svid uvlo (vccl) oc before oc after uvlo (vout) latch uv latch ss latch no fault clearing method recycle vccl ss discharge below 0.2v no outputs affected both single both both single both single single error amp disables yes no ss/delx discharge yes no flags pgood yes delays 32 clock pulses no 8 phsout pulses no 250ns blanking time no no phsout pulses* ss/delx discharge threshold no additional flagged response no yes, iinx and rosc pins pulled-up to vccl** no * pulse number range depends on rosc value selected (see specifications table) ** clears when ov condition ends table 5 shows ir3504 system fault responses downloaded from: http:///
ir3504 page 27 july 28, 2009 applications information css/del2 rvdac2 cvdac2 ishare2 vddnbsen- ccp22 ccp21 rcp2 vdd 5-phase converter vddnb converter cin5 rdrp11 l5 q12 csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 phase ic u11 cvcc2 0.1uf q22 csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 phase ic u21 u32 u51 ccs2 css/del1 cin4 rfb13 ccs1 cvccl phsout rcs5 cvccl4 csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 phase ic u51 l2 cfb1 cvccl6 l1 rdrp12 cbst1 rcs4 q62 cvcc6 q41 rcs1 cvcc5 cvccl3 rfb12 u52 rcp1 cbst61 ccp12 ccs6 q42 q21 rocset1 ccs4 cbst4 cvccl1 0.1uf cin6 rvccldrv cvccl2 v2ea cin1 cvcc4 q11 cin3 u31 cin2 rcs6 cbst3 rvcclfb2 q61 ccs5 csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 phase ic u41 l3 l4 csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 phase ic u6 vdac csin- 15 vcc 13 eain 16 ishare 1 sw 12 gateh 11 boost 10 csin+ 14 dacin 2 clkin 6 phsin 4 phsout 5 gatel 8 pgnd 7 vccl 9 lgnd 3 ir3505 phase ic u31 ccs3 cvcc3 rosc cvcc1 cvccl5 rvdac1 cdrp1 rvcclfb1 q1 cvdac1 cbst5 ccp11 l6 rfb11 cbst3 rtherm1 rcs2 rcs3 12v svd pwrok svc vddpwrgd rfb21 cfb2 rfb22 phsout 26 pwrok 2 enable 3 svc 32 iin2 4 ocset2 7 vosns1+ 14 vdrp1 22 pg 31 iin1 21 clkout 25 vcclfb 29 vccl 28 phsin 27 vosns2- 12 eaout1 17 vout1 15 vdac1 19 vdac2 6 fb2 9 rosc 23 lgnd 24 svd 1 fb1 16 vccldrv 30 ss/del1 20 vout2 10 ocset1 18 vonsn1- 13 vosns2+ 11 ss/del2 5 eaout2 8 ir3504 control ic u1 enable vdd+ vdd- vdd sense- vdd sense+ vddsen+ vddsen- cout vddnb+ vddnb sense+ vddnb- vddnb sense- vddnbsen- vddnbsen+ coutnb phsin vddsen- vddsen+ v2ea vdac2 rocset2 vddea clkout vgate vddnbsen+ close to power stage figure 17 ir3504 \ ir3505 five phases ? one phase d ual outputs amd svid converter downloaded from: http:///
ir3504 page 28 july 28, 2009 design procedures - ir3504 and ir3505 chipset ir3504 external components all the output components are selected using one ou tput but suitable for both unless otherwise specifi ed. oscillator resistor r r osc the ir3504 generates square-wave pulses to synchron ize the phase ics. the switching frequency of the e ach phase converter equals the phsout frequency, which is set by the external resistor r rosc , use figure 2 to determine the r rosc value. the clkout frequency equals the switching fr equency multiplied by the phase number. soft start capacitor c ss/del the soft start capacitor c ss/del programs four different time parameters, soft star t delay time, soft start time, vr ready delay time and over-current fault latch delay time after vr ready. ss/del pin voltage controls the slew rate of the co nverter output voltage, as shown in figure 11. once the enable pin rises above 1.65v, there is a soft-start delay time td1 during which ss/del pin is charged from zero to 1.4v. once ss/del reaches 1.4v the error am plifier output is released to allow the soft start. the soft start time td2 represents the time during which con verter voltage rises from zero to pre-pwrok vid vol tage and the ss/del pin voltage rises from 1.4v to pre-pwrok vid voltage plus 1.4v. vr ready delay time td3 is the time period from vr reaching the pre-pwrok vid volt age to the vr ready signal being issued. calculate c ss/del based on the required soft start time td2. pwrok pre pwrok pre chg del ss v td v i td c ? ? ? = = 6 / 10 * 50 *2 *2 (1) the soft start delay time td1 and vr ready delay ti me td3 are determined by equation (2) and (3) respe ctively. 6 / / 10 * 50 1.1* 1.1* 1 ? = = del ss chg del ss c i c td (2) 6 / / 10 * 50 )1.1 92.3(* )1.1 92.3(* 3 ? ? ? ? ? = ? ? = pwrok pre del ss chg pwrok pre del ss v c i v c td (3) once c ss/del is chosen, use equation (4) to calculate the maxim um over-current fault latch delay time t ocdel. 6 / / 10 * 47 13.0* *5.2 13.0* *5.2 ? = = del ss dischg del ss ocdel c i c t (4) due to the exponential turn-on slope of the dischar ge current (47ua), a correction factor (x2.5) is ad ded to the equation (4) to accurately predict over-current del ay time. downloaded from: http:///
ir3504 page 29 july 28, 2009 vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by the external capacitor c vdac as defined in (5), where i sink is the sink current of vdac pin. the slew rate of v dac up-slope is three times greater that of down-slope. the resistor r vdac is used to compensate vdac circuit and is determin ed by (6). down sink vdac sr i c = (5) 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (6) over current setting resistor r ocset the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the su m of input offset (v cs_ofst) of the amplifier itself and that created by the am plifier input bias current flowing through the curr ent sense resistor r cs . cs csin ofst cs tofst cs r i v v ? + = + _ _ (7) the inductor dc resistance is utilized to sense the inductor current. r l is the inductor dcr. the over current limit is set by the external resis tor r ocset as defined in (9). i limit is the required over current limit. i ocset is the bias current of ocset pin and can be calcul ated with the equation in the electrical characteristics table. g cs is the gain of the current sense amplifier. k p is the ratio of inductor peak current over average current in each phase and can be calcu lated from (10). ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ _ ? + + ? ? = (9) n i f v l v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? = (10) vccl programming resistor r vcclfb1 and r vcclfb2 since vccl voltage is proportional to the mosfet ga te driver loss and inversely proportional to the mosfet conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. vcc l linear regulator consists of an external npn transi stor, a ceramic capacitor and a programmable resist or divider. pre-select r vcclfb1 , and calculate r vcclfb2 from (11). 23.1 23.1* 1 2 ? = vccl r r vcclfb vcclfb (11) downloaded from: http:///
ir3504 page 30 july 28, 2009 no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r as the effective offset resistor at room temperatur e equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst (offset above the dac voltage) and calculating the sink current from the fb1 pin i fb1 using the equation in the electrical characteristic s table, the effective offset resistor value, r fb1, can be determined from (12). 1 _ _ fb nlofst o r fb i v r = (12) adaptive voltage positioning lowers the converter v oltage by r o *i o where r o is the required output impedance of the converter. pre-select feedback resistor r fb and calculate the droop resistor rdrp, . * _ _ 11 o cs room l r fb drp r n g r r r ? ? = (13) calculate the desired effective feedback resistor a t the maximum temperature r fb_m using (14). max l cs o drp m fb r g n r r r _ 11 _ * ? ? = (14) a negative temperature constant (ntc) thermistor r therm1 is required to sense the temperature of the power stage for the inductor dcr thermal compensation. pr e-select the value of r therm. r therm must be bigger than r fb_r at room temperature but also bigger than r fb_m at the maximum allowed temperature. r tmax1 is defined as the ntc thermistor resistance at maximum allowed temperature, t max. r tmax1 is calculated from (15). )] 1 1 (* [ * _ _ 1 1 1 room max l therm therm tmax t t b exp r r ? = (15) select the series resistor r fb13 by using equation (16). r fb13 is incorporated to linearize the ntc thermistor which has non-linear characteristics in the operati onal temperature range. 2 ) ( )) /( * *) ( * (*4 ) ( 1 1 _ _ _ _ 1 1 1 1 2 1 1 13 tmax therm m fb rfb m fb rfb tmax therm tmax therm tmax therm fb t r r r r r r r r r r r r + ? ? ? ? ? + = (16) use equation (17) to determine r fb11. 1 13 _ 11 1 1 1 therm fb r fb fb r r r r + ? = (17) downloaded from: http:///
ir3504 page 31 july 28, 2009 ir3505 external components inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore th e voltage across the capacitor c cs represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different fro m that of the real inductor current. the time const ant mismatch does not affect the average current sharing among t he multiple phases, but affect the current signal i share as well as the output voltage during the load current transient if adaptive voltage positioning is adopte d. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c rl r = (21) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are required at vcc and vccl pins of phase ics. downloaded from: http:///
ir3504 page 32 july 28, 2009 voltage loop compensation the adaptive voltage positioning (avp) is usually a dopted in the computer applications to improve the transient response and reduce the power loss at heavy load. l ike current mode control, the adaptive voltage posi tioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which m ake the voltage loop compensation much easier. adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. the selection of compensation types depends on the output capacitors used in the converter. for the ap plications using electrolytic, polymer or al-polymer capacitor s and running at lower frequency, type ii compensat ion shown in figure 21(a) is usually enough. while for the ap plications using only ceramic capacitors and runnin g at higher frequency, type iii compensation shown in figure 21 (b) is preferred. for applications where avp is not required, the com pensation is the same as for the regular voltage mo de control. for converter using polymer, al-polymer, a nd ceramic capacitors, which have much higher esr z ero frequency, type iii compensation is required as sho wn in figure 21(b) with r drp and c drp removed. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 18. voltage loop compensation network type ii compensation for avp applications determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capaci tor across the output inductors matches that of the inductor, and determine r cp and c cp from (23) and (24), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. 2 2 ) * * * 2( 1 * 5 ) 2( c c i fb e e c cp r c f v r c l f r + ? ? ? ? ? = (23) cp e e cp r c l c ? ? = 10 (24) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. downloaded from: http:///
ir3504 page 33 july 28, 2009 type iii compensation for avp applications determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by (25) and (26), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f ? ? = * * 2 1 (25) 180 )5.0 tan( 90 1 ? ? = a c (26) choose the desired crossover frequency fc around fc 1 estimated by (25) or choose fc between 1/10 and 1 /5 of the switching frequency per phase, and select the c omponents to ensure the slope of close loop gain is -20db /dec around the crossover frequency. choose resisto r r fb1 according to (27), and determine c fb and c drp from (28) and (29). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (27) 1 4 1 fb c fb r f c ? ? = (28) drp fb fb fb drp r c r r c ? + = ) ( 1 (29) r cp and c cp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequency and transient load response. determine r cp and c cp from (30) and (31). i fb e e c cp v r c l f r 5 ) 2( 2 ? ? ? ? ? = (30) cp e e cp r c l c ? ? = 10 (31) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. type iii compensation for non-avp applications resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the de sired phase margin c. calculate k factor from (32), and determine the component values based on (33) to (37 ), )]5.1 180 ( 4 tan[ + ? = c k (32) k v f c l r r i c e e fb cp ? ? ? ? ? ? = 5 ) 2( 2 (33) cp c cp r f k c ? ? = 2 (34) cp c cp r k f c ? ? ? = 2 1 1 (35) downloaded from: http:///
ir3504 page 34 july 28, 2009 fb c fb r f k c ? ? = 2 (36) fb c fb c k f r ? ? ? = 2 1 1 (37) current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so t hat the interaction between the two loops is elimin ated. downloaded from: http:///
ir3504 page 35 july 28, 2009 design example ? amd five + one phase dual output c onverter (figure 17) specifications input voltage: v i =12 v dac voltage: v dac =1.2 v no load output voltage offset for output1: v o_nlofst =15 mv output1 current: i o1 =95 adc output2 current: i o1 =20 adc output1 over current limit: i limit1 =115 adc output2 over current limit: i limit2 = 25 adc output impedance: r o1 =0.3 m dynamic vid slew rate: sr=3.25mv/us over temperature threshold: t max =110 oc power stage phase number: n1=5, n2=1 switching frequency: f sw =520 khz output inductors: l1=120 nh, l2=220 nh, r l1 = 0.52m , r l2 = 0.47m output capacitors: poscaps, c=470uf, r c = 8m , number cn1=9, cn2=5 ir3500 external components oscillator resistor r rosc once the switching frequency is chosen, r rosc can be determined from figure 2. for switching frequency of 520khz per phase, choose r osc =23.2k . soft start capacitor c ss/del determine the soft start capacitor from the require d soft start time. uf vboot i td c chg del ss 1.0 0 . 1 10 * 50 * 10 *2 *2 6 3 / = = = ? ? the soft start delay time is ms i c td chg del ss 2.2 10 * 50 1.1* 10 *1.0 1.1* 1 6 6 / = = = ? ? the vr ready delay time is ms i v c td chg boot del ss 6.3 10 * 50 )1.1 1 92.3(* 10 *1.0 )1.1 92.3(* 3 6 6 / = ? ? = ? ? = ? ? the maximum over current fault latch delay time is ms i c t dischg del ss ocdel 691 .0 10 * 47 13.0* 10 *1.0 *5.2 13.0* *5.2 6 6 / = = = ? ? downloaded from: http:///
ir3504 page 36 july 28, 2009 vdac slew rate programming capacitor c vdac and resistor r vdac nf sr i c down sink vdac 1.14 10*2.3 10 2.45 3 6 = ? = = ? , choose c vdac =22nf ohm c r vdac vdac 1.7 10 2.3 5.0 2 15 = ? + = ? over current setting resistor r ocset the output1 over current limit is 115a and the outp ut2 over current limit is 25a. from the electrical characteristics table can get the bias current of ocset pin (i ocset ) is 26ua with r osc =23.2 k . the total current sense amplifier input offset voltage is around 0mv, calcu late constant k p, the ratio of inductor peak current over average current in each phase, 38.0 5/ 115 )2 10* 520 12 10* 120 /(2.1)2.1 12( / )2 /( ) ( 1 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p 19.0 25 )2 10* 520 12 10* 220 /(2.1)2.1 12( 2 3 9 = ? ? ? ? ? = ? p k ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 1 _ ? + + ? ? = ? = ? ? = ? ? k 6.21 ) 10*26 /( 34*)38.1 10*52.0 5 115 ( 6 3 ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 2 _ ? + + ? ? = ? = ? ? = ? ? k 4.18 ) 10*26 /( 34*)19.1 10*47.0 1 25 ( 6 3 vccl programming resistor r vcclfb1 and r vcclfb2 choose vccl=7v to maximize the converter efficiency . pre-select r vcclfb1 =20k , and calculate r vcclfb2. ? = ? = ? = k vccl r r vcclfb vcclfb 26.4 23.1 7 23.1* 10*20 23.1 23.1* 3 1 2 no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r is the effective offset resistor at room temperatur e equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst above the dac voltage, calculate the sink current f rom the fb1 pin i fb1 = 26ua using the equation in the electrical characteristics tabl e, then the effective offset resistor value r fb_r 1 can be determined by: ohm i v r fb nlofst o r fb 577 10*26 10*15 1 6 3 1 _ _ = = = ? ? adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, downloaded from: http:///
ir3504 page 37 july 28, 2009 kohm r n g r r r o cs room l r fb drp 7.6 10*3.0*5 34* 10*52.0* 577 * 1 3 3 _ _ = = ? ? = ? ? in the case of thermal compensation is required, us e equation (14) to (17) to select the r fb network resistors. ir3505 external components inductor current sensing capacitor c cs and resistor r cs choose c cs 1=c cs 2=0.1uf, and calculate r cs, ? = = = ? ? ? k c rl r cs l cs 3.2 10*1.0 ) 10*52.0/( 10* 120 1 6 3 9 ? = = = ? ? ? k c rl r cs l cs 7.4 10*1.0 ) 10*47.0/( 10* 220 2 6 3 9 downloaded from: http:///
ir3504 page 38 july 28, 2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. dedicate at least one middle layer for a ground pl ane lgnd. connect the ground tab under the control ic to lgn d plane through a via. separate analog bus (eain, dacin and ishare) from digital bus (clkin, phsin, and phsout) to reduce the noise coupling. place vccl decoupling capacitor vccl as close as p ossible to vccl and lgnd pins. place the following critical components on the sam e layer as control ic and position them as close as possible to the respective pins, rosc, rocset, rvda c, cvdac, and css/del. avoid using any via for the connection. place the compensation components on the same laye r as control ic and position them as close as possi ble to eaout, fb, vo and vdrp pins. avoid using any via for the connection. use kelvin connections for the remote voltage sens e signals, vosns+ and vosns-, and avoid crossing ov er the fast transition nodes, i.e. switching nodes, ga te drive signals and bootstrap nodes. avoid analog control bus signals, vdac, iin, and e specially eaout, crossing over the fast transition nodes. separate digital bus, clkout, phsout and phsin fro m the analog control bus and other compensation components. downloaded from: http:///
ir3504 page 39 july 28, 2009 pcb metal and component placement lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) a single 0.30mm diameter via shall be placed in th e center of the pad land and connected to ground to minimize the noise effect on the ic. no pcb traces should be routed nor vias placed und er any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resulting in poor solder joints to the ic leads. downloaded from: http:///
ir3504 page 40 july 28, 2009 solder resist the solder resist should be pulled away from the m etal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where th e lead land groups meet, it is recommended to provi de a fillet so a solder resist width of 0.17mm remains. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist m is-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. the single via in the land pad should be tented or plugged from bottom boardside with solder resist. downloaded from: http:///
ir3504 page 41 july 28, 2009 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the s tencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open . the maximum length and width of the land pad stenc il aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decreas e the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3504 page 42 july 28, 2009 package information 32l mlpq (5 x 5 mm body) ja =24.4 o c/w, jc =0.86 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . www.irf.com downloaded from: http:///

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